CISCO GSR与Juniper骨干路由器比较

CISCO 千兆交换路由器(GSR)体系结构
Cisco 12012 全交换总线结构
CISCO GSR仍然是基于对传统路由器的改进，增强了路由器处理器（RP）和增加了专用的ASIC接口处理器。采用接口分布式处理和单一（或冗余）的CPU处理，仍然基于总线结构。
GSR 接口卡
GSR 路由处理器

采用RISC 处理器：
IDT R5000 RedUCed Instruction Set Computing (RISC) processor used for the CPU. The CPU runs at an external bus clock speed of 100 MHz and an internal clock speed of 200 MHz.
配置内存包括：
DRAMM—Up to 256 megabytes (MB) of parity-protected, extended data output (EDO) dynamic random-Access memory (DRAM) on two, 60-nanosecond (ns), dual in-line memory modules (DIMMs). 128 MB of DRAM is the minimum shipping configuration for the GRP.
　SRAM—512 kilobytes (KB) of static random-access memory (SRAM) for secondary CPU cache memory functions. (SRAM is not user configurable or field upgradeable.)
NVRAM—512 KB of nonvolatile RAM (NVRAM). (NVRAM is not user configurable or field upgradeable.)
Memory—Most of the additional memory components used by the system, including onboard Flash memory and up to two Personal Computer Memory Card International Association (PCMCIA)-based Flash memory cards.
Juniper骨干路由器体系结构
体系结构
两个要害部件：Packet Forwarding Engine (PFE)、Routing Engine，, which are connected via a 100-Mbps link.
_ PFE完成分组的转发，包括Flexible PIC Concentrators (FPCs), physical interface cards (PICs), System Control Board (SCB), and state-of-the-art ASICs.
_ Routing Engine维护路由表，控制路由选择协议。Intel-based PCI platform running JUNOS software.
Leading-edge ASICs
ASICs deliver a comprehensive hardware-based system for packet processing, including route lookups, filtering, sampling, rate limiting, load balancing, buffer management, switching, encapsulation, and de-encapsulation functions. To ensure a non-blocking forwarding path, all channels between the ASICs are oversized, dedicated paths.
Internet Processor II ASIC
The Internet Processor II? ASIC supports a lookup rate of over 40 Mpps. With over one million gates, the Internet Processor II ASIC delivers high-speed forwarding performance with advanced services, such as filtering and sampling, enabled. It is the largest, fastest, and most advanced ASIC ever implemented on a router platform and deployed in the Internet.
Distributed Buffer Manager ASICs
The Distributed Buffer Manager ASICs allocate incoming data packets throughout shared memory on the FPCs. This singlestage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers. The shared memory is completely nonblocking, which in turn, prevents head-of-line blocking.
I/O Manager ASICs
Each FPC is equipped with an I/O Manager ASIC that supports packet parsing, packet prioritizing, and queuing. This ASIC divides the packets, stores them in shared memory (managed by the Distributed Buffer Manager ASICs), and reassembles the packets for transmission.
Media-specific ASICs
The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC’s media type.
Packet Forwarding Engine
The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding. The Internet Processor II ASIC forwards up to 40 Mpps for all packet sizes. The throughput is 40Gbps.
The PFE supports the same ASIC-based features supported by other M-series routers. For example, class-of-service features include rate limiting, classification, priority queuing, Random Early Detection, and Weighted Round Robin to increase bandwidth efficiency. Filtering and sampling are also available for restricting access, increasing security, and analyzing network traffic.